In digital electronics, a debouncing circuit is essential for stabilizing the output of mechanical switches. Due to the physical nature of switches, pressing or releasing them can produce a noisy signal consisting of rapid on-off states (bounce effects), which can lead to multiple unwanted triggers. A debouncing circuit filters out these fluctuations and produces a clean, stable output.
Task:
Implement a debouncing circuit in Verilog that stabilizes an input signal from a mechanical switch. The circuit should output a clean, stable high signal only after the input has been high continuously for a specific duration, effectively filtering out any bounce effects.
Requirements:
Module Interface:
-Inputs:
input clk: Clock input.
input reset: Asynchronous reset input, active high.
input noisy_signal: The noisy input signal from a mechanical switch.
-Outputs:
output reg stable_signal: The debounced output signal.
Parameters:
DEBOUNCE_TIME: A parameter to specify the debounce duration in clock cycles.
Functionality:
The debouncing circuit should monitor noisy_signal. If noisy_signal remains high for a continuous duration of DEBOUNCE_TIME clock cycles, stable_signal should be set high.
If noisy_signal goes low at any point before DEBOUNCE_TIME clock cycles have elapsed, the counter should reset.
The stable_signal should return to low immediately when noisy_signal goes low.
The circuit should also be resettable by an asynchronous reset signal.
Additional Instructions:
Consider the clock frequency and desired debounce duration to set an appropriate DEBOUNCE_TIME.
Your implementation will be evaluated on correctly outputting a stable high signal under debounce conditions and resetting appropriately.
